When terminal devices such as a PC (Personal Computer, personal computer) and a common server are used for accessing a network, for example, browsing a web page, network traffic is usually increased rapidly at the instant that the website is clicked, and the traffic is reduced after the web page is loaded. During the browsing process, generally the network traffic is not required. For the pulse type changing feature of the network traffic, the EEE (Energy Efficient Ethernet, energy efficient Ethernet) standard is proposed in the prior art so that dynamic energy-saving is implemented according to the feature of the network traffic. The network traffic is usually transmitted based on the Internet layer, where physical signal conversion is performed on a PHY layer, and when no data is transmitted on a MAC (Media Access Control, media access control) layer, training data is transmitted as little as possible on the PHY layer, or no training data is transmitted, to achieve the object of energy saving.
When no data is transmitted on the MAC layer, and an IDLE (idle) signal is transmitted on the PHY layer, the network is in ACTIVE (active) mode. In this case, the MAC layer transmits an LPI (Low Power Idle, low power mode) request signal. The PHY layer enters a QUIET (quiet) state after receiving the signal. In the QUIET state, no signal is transmitted over the link, thereby achieving energy saving. However, in order to keep synchronization performance with a communication peer end when the ACTIVE state is entered, a REFRESH (REFRESH) state needs to be periodically inserted into the QUIET state, so that the terminal is capable of keeping synchronization performance with the communication peer end according to the training signal from the communication peer end.
In the prior art, in the REFRESH state, the terminal is required to implement clock synchronization within a preset time of period (usually 16.5 microseconds) by using a built-in CDR circuit. In the clock synchronization process, an input phase signal of a loop filter in the CDR circuit is controlled by using two state signals, so that the clock synchronization is implemented after phase convergence. However, in the prior art, after the terminal receives the refresh signal from the peer end, if frequency deviation between two communication parties is large, the phase convergence process is controlled by using two state signals, which results in a slow convergence speed. Therefore, the terminal can hardly implement clock synchronization with the peer end within the preset time of period, and thus the terminal cannot receive data from the communication peer end when entering the ACTIVE mode.